Simulation and timing analyses of VHDL models of coder and decoder of duobinary pulse position modulation

Duobinary Pulse Position Modulation (DuoPPM) has been proposed as an alternative novel coding
scheme which manifests many advantages over currently existing PPM formats according to the
preliminary results obtained from theory and simulations run by one of the authors, Sibley. It combines the bandwidth reduction of the three-level duobinary code with the dispersion characteristics of conventional PPM. This coding is intended to be implemented using VHDL (VHSIC hardware description language) and an FPGA (Field-programmable gate array) over Plastic Optical Fibre (POF). Nevertheless if the preliminary promises of this new coding scheme are fulfilled upon successful implementation, it may be adapted to high-speed optical communications links. For the first time, the original VHDL designs, simulation results and timing analyses of DuoPPM coder and decoder are presented in this paper. These design developments are the fundamental circuits required for further investigation of this proposed coding scheme.