Extended update plans

Formal methods are gaining popularity as a way of increasing the reliability of systems through
the use of mathematically based techniques. Their domain is no longer restricted to purely
academic environments and examples, as they are slowly moving into industrial settings. The
slow rate at which this transition takes place is mainly due to the perceived difficulty of
formalising the behaviour of systems. While this is undoubtedly true, it is not the case with
all formal methods.

Update Plans are a powerful formalism for the description of computer architectures
and intermediate to low-level languages. They are a declarative specification language with
an underlying imperative machine model. The descriptions using Update Plans are clear,
compact, intuitive, unambiguous and simple to read. These characteristics allow for the
minimisation of possible errors at early stages of the development process even before a
verification takes place.

In this thesis an overview of the Update Plans formalism is given and a number of realworld
applications is shown. The investigation of the application area focuses on computer
architectures for which various specifications already exist. The comparison of Update Plan
specifications to other specifications provides a useful insight into the strengths and shortcomings
of the formalism. The shortcomings, in particular the lack of synchronisation primitives
and modularity, are addressed by the development and evaluation of several syntactic and
semantic extensions described in this thesis. The extended formalism is also compared to
other specification languages and conclusions are drawn.