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Built-in-self-test of analogue circuits using optimised fault sets and transient response testing

Axelos, N., Watson, J., Taylor, D. and Platts, A. (2002) Built-in-self-test of analogue circuits using optimised fault sets and transient response testing. On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International. pp. 135-139. ISSN 0-7695-1641-6

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Transient Response Testing has been shown to be a very powerful and economical functional test technique for linear analogue cells in mixed-signal systems. Recently this work has been extended to non-linear analogue circuits by treating Transient Response Testing as a structural test technique and employing optimised and reduced fault sets that are derived from Inductive Fault Analysis and circuit sensitivity analyses. These developments have been very successful and have also facilitated a novel BIST methodology for analogue circuits. The BIST scheme employs a generic on-chip stimulus for all analogue cells and features a specially designed test cell that coordinates a short test sequence that involves sampling the transient response at key instants in the test cycle and comparing to a known reference.

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Item Type: Article
Additional Information: © Copyright 2002 IEEE
Uncontrolled Keywords: transient response testing linear analogue circuit BIST
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Schools: School of Computing and Engineering
School of Computing and Engineering > High-Performance Intelligent Computing > Visualisation, Interaction and Vision
References: 1. P. S. A. Evans, M. Al Qutayri, P. R. Shepherd, “A Novel Technique for Testing Mixed-Signal ICs”,Proceedings of ITC, 1991, pp301-306 2. D. Taylor, and P.S.A.Evans, and T.I.Pritchard: ‘Testing of Mixed-Signal Systems Using Dynamic Stimuli’, Electron. Letters, 1993, 29, (9), pp811-813 M Sample/Hold VIN VOUTIVOFF M Stimulus Control WIND COMP 3. I. C. Butler, D.Taylor, and T.I.Pritchard: ‘Effects of Response Quantisation on the Accuracy of Transient Response Test Results’, IEE Proceedings Circuits Devices Systems., 1995, 142, (5), pp 334-338 ROM (Pulse Width) (Sample Time) (Sample Value) RE GI T E RSample PASS/ FAIL DAC Compare 4. R. J. Binns, D. Taylor, T. I. Pritchard, "Testing Linear Macros in Mixed-Signal Systems using Transient Response Testing and Dynamic Supply Current Monitoring" IEE Electronics Letters, No.30, Vol. 15 , 21st July 1994, pp 1216-1217 TEST PASS/FAIL CLK 5. R. J. Binns, D. Taylor, T. I. Pritchard, “Generating, Capturing and Processing Supply Current Signatures from Analogue Macros in Mixed-Signal Systems”, The Microlectronics Journal, Vol. 27, 1996. 6. IEEE Standard 1149.1: “Standard Test Access Port and Boundary Scan Architecture”, The Computer Society, IEEE, 1990 7. M. Sachdev, “A defect oriented testability methodology for analog circuits,” Journal of Electronic Testing: Theory and Applications, vol. 6, no. 3, 1995, pp. 265-276. 8. T. Olbrich, J. Perez, I. A. Grout, A.M. Richardson, and C. Ferrer, "Defect-oriented vs Schematic-Level based fault Simulation for Mixed-Signal ICs." IEEE International Test Conference, 1996, pp.511-521. 9. H. Walker and S.W. Director, “VLASIC, A catastrophic fault yield simulator for integrated circuits,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. CAD-5(4), 1986, pp. 541-556. 10. A. Milne, D. Taylor, K. Naylor, “Assessing and Comparing Fault Coverage When Testing Analogue Circuits”, IEE Proceedings Circuits Devices and Systems, Vol. 144, No. 1, 1997, pp1-4. 11. A. Platts, D. Taylor, “Transient Response Testing of Non-Linear Analogue Circuits Using Optimised Fault Sets, Submitted to IEE Proceeding Circuits Devices and Systems.
Depositing User: Sara Taylor
Date Deposited: 16 May 2007
Last Modified: 28 Aug 2021 23:36


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